Semiconductor structures and methods for fabricating semiconductor structures comprising high dielectric constant stacked structures

ABSTRACT

Semiconductor structures, and methods for fabricating semiconductor structures, comprising high dielectric constant stacked structures are provided. A stacked dielectric structure ( 16 ) in accordance with one exemplary embodiment of the present invention has a first amorphous dielectric layer ( 18 ) comprising Hf X Zr 1-X O 2 , where 0≦X≦1. An amorphous interlayer ( 20 ) overlies the first amorphous dielectric layer. The interlayer has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO 4 . A second amorphous dielectric layer ( 22 ) overlies the interlayer. The second amorphous dielectric layer comprises Hf Y Zr 1-Y O 2 , where 0≦Y≦1. The stacked dielectric structure ( 16 ) has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO 4 .

FIELD OF THE INVENTION

The present invention generally relates to semiconductor structures andto methods for their fabrication, and more particularly relates tosemiconductor structures and methods for forming semiconductorstructures comprising stacked layers having high dielectric constants.

BACKGROUND OF THE INVENTION

As future generations of electronic devices advance in complexity anddecrease in size, a growing need exists for a dielectric material moreeffective than SiO₂. Increased demands on ultra-large scale integrated(ULSI) circuits have required that the SiO₂ that forms the gate oxide offield-effect transistors be made laterally smaller and, consequently,thinner. Eventually, however, the SiO₂ layers will be required to be sosmall and thin that electron tunneling will make current leakageunacceptably high for low-power devices.

Hafnium oxide (HfO₂), also known as hafnia, has been identified as apromising candidate to replace SiO₂ as a gate dielectric. Hafnium oxide,having a relatively high bulk dielectric constant (k=15–25), would allowgate oxides to be physically thicker (for a given capacitance), whichcould significantly reduce tunneling. Hafnium oxide also exhibits alarge band gap (approximately 5.7 eV) and a band offset (greater than 1eV) with substrates such as silicon. Further, the diffusion of hafniumatoms into substrates such as silicon, particularly during or afterpost-deposition anneals, has proven to be negligible.

However, when sufficiently thick, an amorphous hafnium oxide film tendsto crystallize at relatively low temperatures (approximately 400° C.) toform monoclinic, cubic, and/or tetragonal crystallites. Polycrystallinehafnium oxide facilitates unwanted metal or impurity diffusion throughgrain boundaries and degrades gate stack performance. Polycrystallinehafnium oxide also causes higher leakage current because of chargetransport through grain boundaries. Further, the surface ofpolycrystalline hafnium oxide may have grains with differentterminations associated with different surface potentials due todifferent dipole strength and orientation of the terminations. Suchvaried surface potentials could be detrimental to device yield if thevariation of the surface potential is sufficiently large and the grainsizes are comparable to gate dimensions.

Accordingly, it is desirable to provide a semiconductor structure and amethod for fabricating a semiconductor structure without the undesirabledrawbacks described above. Furthermore, other desirable features andcharacteristics of the present invention will become apparent from thesubsequent detailed description of the invention and the appendedclaims, taken in conjunction with the accompanying drawings and thisbackground of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will hereinafter be described in conjunction withthe following drawing figures, wherein like numerals denote likeelements, and

FIG. 1 is a cross-sectional view of a semiconductor structure inaccordance with an exemplary embodiment of the present invention;

FIG. 2 is a cross-sectional view of a semiconductor structure inaccordance with another exemplary embodiment of the present invention;

FIG. 3 is a cross-sectional view of a semiconductor structure inaccordance with a further exemplary embodiment of the present invention;

FIG. 4 is a graphical representation of an energy band alignment of asemiconductor structure having a silicon substrate, a silicon oxidelayer overlying the substrate, a hafnium oxide layer overlying thesilicon oxide layer, and a metal layer overlying the hafnium oxidelayer;

FIG. 5 is a graphical representation of an energy band alignment of asemiconductor structure having a silicon substrate, a silicon oxidelayer overlying the substrate, a graded dielectric structure overlyingthe silicon oxide layer, and a metal layer overlying the hafnium oxidelayer;

FIG. 6 is a flowchart of a process for fabricating a semiconductorstructure in accordance with an exemplary embodiment of the presentinvention; and

FIG. 7 is a cross-sectional view of a conventional field effecttransistor.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description of the invention is merely exemplaryin nature and is not intended to limit the invention or the applicationand uses of the invention. Furthermore, there is no intention to bebound by any theory presented in the preceding background of theinvention or the following detailed description of the invention.

FIG. 1 illustrates schematically, in cross section, a portion of asemiconductor structure 10 in accordance with an exemplary embodiment ofthe present invention. Semiconductor structure 10 may be, for example, aportion of a MOS or CMOS field effect transistor or may comprise anyother suitable circuit comprising a dielectric material. For purposes ofexample, FIG. 7 illustrates a conventional MOS field effect transistor250. Transistor 250 is formed on a substrate 252 and comprises a sourceregion 254, a drain region 256, and a channel region 258 overlying whichis a dielectric structure 260. An electrode 262 is formed overlyingdielectric structure 260.

As stated above, semiconductor structure 10 may be a portion of a fieldeffect transistor, as illustrated in FIG. 1, where, for purposes ofsimplicity, the source and drain regions are not shown. Alternatively,semiconductor structure 10 may comprise any other suitable circuit.Semiconductor structure 10 comprises a substrate 12, such as substrate252 of FIG. 7, which may comprise any suitable semiconductor, compoundsemiconductor, or metal. The substrate can be of, for example, amaterial from Group IV of the Periodic Table. Examples of Group IVsemiconductor materials include silicon, germanium, mixed silicon andgermanium, mixed silicon and carbon, and the like. Substrate 12 also maycomprise other substrates commonly used in the semiconductor industry,such as, for example, gallium arsenide. Substrate 12 also may comprise ametal, such as platinum, molybdenum, copper or aluminum, as required fora particular device application, such as a metal-insulator-metalapplication. In a preferred embodiment of the invention, substrate 12comprises silicon.

In one embodiment of the invention, semiconductor structure 10 also maycomprise an amorphous oxide layer 14 overlying substrate 12. In apreferred embodiment of the invention, oxide layer 14 comprises asilicon oxide SiO_(X), where X is any number greater than zero. Theoxide layer 14 may have any suitable thickness that does not adverselyaffect the dielectric constant of an overlying amorphous dielectricstructure 16, discussed in more detail below. Preferably, oxide layer 14has a thickness in the range of about 0.5 nanometers to about 1nanometer. Oxide layer 14 serves as a barrier to diffusion of materialsinto substrate 12, forms a superior interface with substrate 12, andprovides an amorphous foundation upon which dielectric structure 16 maybe formed.

As described above, semiconductor structure 10 further comprisesamorphous dielectric stacked structure 16 overlying substrate 12.Dielectric structure 16 may comprise, for example, the gate oxide of aMOS or CMOS field effect transistor, such as dielectric structure 260 ofFIG. 7. Dielectric structure 16 is formed of a first amorphousdielectric layer 18, an amorphous interlayer 20, and a second amorphousdielectric layer 22. Dielectric structure 16 may have any thicknesssuitable for minimizing or eliminating tunneling through dielectricstructure 16. Preferably, dielectric structure 16 has a thickness in therange of about 1 nanometer to about 10 nanometers and, more preferably,has a thickness in the range of about 3 to about 4 nanometers. In oneembodiment of the invention, semiconductor structure 10 also maycomprise an electrode 24, such as electrode 262 of FIG. 7, that isdisposed overlying amorphous dielectric structure 16.

First amorphous dielectric layer 18 may comprise amorphous HfO₂,zirconium oxide (ZrO₂), or an alloy having the formula Hf_(X)Zr_(1-X)O₂,where 0≦X≦1, and has a dielectric constant k₁ that is approximately noless than the dielectric constant of HfZrO₄. In a preferred embodimentof the invention, first amorphous dielectric layer 18 comprises HfO₂.

Second amorphous dielectric layer 22 may comprise amorphous HfO₂, ZrO₂,or an alloy material having the formula Hf_(Y)Zr_(1-Y)O₂, where 0≦Y≦1,and also has a dielectric constant k₂ that is approximately no less thanthe dielectric constant of HfZrO₄. In one embodiment of the invention,first and second amorphous dielectric layers 18 and 22 are formed ofdifferent materials, that is, X does not equal Y and/or k₁ does notequal k₂. In another embodiment of the invention, first and secondamorphous dielectric layers 18 and 22 are formed of the same materials,that is, X is approximately equal to Y and k₁ is approximately equal tok₂. In a preferred embodiment of the invention, first amorphousdielectric layer 18 and second amorphous dielectric layer 22 compriseHfO₂. Amorphous dielectric layers 18 and 22 each have a thickness thatis less than a thickness at which polycrystalline phases may form.

Interlayer 20 may comprise any amorphous dielectric material orcombination of materials that has a chemical composition that isdifferent from first and/or second dielectric layers 18 and 22 and thatresults in interlayer 20 having a net dielectric constant k₃ that isapproximately no less than the dielectric constant of HfZrO₄. Materialssuitable for forming interlayer 20 include, but are not limited to,lanthanum aluminum oxide (La_(X)Al_(Y)O₃), lanthanum scandium oxide(La_(X)Sc_(Y)O₃), lanthanum lutetium oxide (La_(X)Lu_(Y)O₃), strontiumtitanate (Sr_(X)Ti_(Y)O₃), barium titanate (Ba_(X)Ti_(Y)O₃), strontiumbarium titanate (Sr_(X)Ba_(Y)Ti_(Z)O₃), barium zirconium oxide(Ba_(X)Zr_(Y)O₃), strontium zirconium oxide (Sr_(X)Zr_(Y)O₃), andtantalum oxide (Ta₂O₅), where X, Y and Z are any numbers greater thanzero. Interlayer 20 may comprise one continuous layer or may comprisemultiple sublayers. Interlayer 20 has a thickness that is less than athickness at which polycrystalline phases may form.

The use of an interlayer 20 interposed between first and secondamorphous dielectric layers 18 and 22 permits the stacked dielectricstructure 16 to have a thickness that minimizes or eliminates tunnelingthrough dielectric structure 16 while also preventing or minimizing theformation of polycrystalline phases within dielectric structure 16. Inaddition, the use of the thin amorphous layers in the stacked structureresults in an increase the crystallization onset temperature of theentire dielectric stack 16, thus improving the stability and uniformityof the amorphous dielectric stack 16 during subsequent anneal processes.Further, the use of an interlayer 20 having a dielectric constant k₃ ofabout no less than the dielectric constant of HfZrO₄ maintains anoverall dielectric constant k_(TOTAL) of dielectric stack 16 at aboutthe dielectric constant of HfZrO₄ or may even increase the dielectricconstant of the dielectric stack 16 above the dielectric constant ofHfZrO₄. For example, interlayer 20 may comprise BaSrTiO₃, which has adielectric constant of approximately 300. When disposed betweenamorphous dielectric layers 18 and 22 that are formed of HfO₂, theBaSrTiO₃ interlayer 20 serves to increase the dielectric constantk_(TOTAL) of dielectric stack 16 above that of HfO₂. In addition tomodifying the crystallization temperature and the dielectric constant,the presence of an interlayer, such as layer 20 in FIG. 1, also maymodify oxygen transport behavior of the overall dielectric stack andsubsequently allow for better control of the thickness of theinterfacial SiO_(X) layer 14 during subsequent material/deviceprocessing steps.

It will be appreciated that a semiconductor structure in accordance withanother embodiment of the present invention may comprise multipleinterlayers disposed between amorphous dielectric layers. Referring toFIG. 2, a semiconductor structure 50 may comprise a substrate 12 and anoxide layer 14, such as substrate 12 and oxide layer 14 described abovewith reference to FIG. 1. Semiconductor structure 50 may also be cappedwith an electrode 24, such as electrode 24 described above withreference to FIG. 1. Semiconductor structure 50 further may comprise anamorphous dielectric stacked structure 52 overlying oxide layer 14.Dielectric structure 52 may comprise, for example, the gate oxide of aMOS or CMOS field effect transistor, such as dielectric structure 260 ofFIG. 7. Dielectric structure 52 is formed of a first amorphousdielectric layer 54, a second amorphous dielectric layer 56, and a thirdamorphous dielectric layer 58. First amorphous dielectric layer 54,second amorphous dielectric layer 56, and third amorphous dielectriclayer 58 each may be formed of any of the materials used to form firstand/or second dielectric layers 18 and 22 described above and may beformed of the same or different materials. Dielectric structure 52further comprises a first interlayer 60 interposed between first andsecond amorphous dielectric layers 54 and 56 and a second interlayer 62interposed between second and third amorphous dielectric layers 56 and58. First interlayer 60 and second interlayer 62 each may be formed ofany of the materials used to form interlayer 20 described above and maybe formed of the same or different materials. Dielectric structure 52may have any thickness suitable to reduce or minimize tunneling throughdielectric structure 52. Preferably, dielectric structure 52 has athickness in the range of about 1 nanometer to about 10 nanometers and,more preferably, has a thickness in the range of about 3 to about 4nanometers. It will be appreciated that, while FIG. 1 illustrates astacked dielectric structure 16 comprised of three layers and FIG. 2illustrates a stacked dielectric structure 52 comprised of five layers,the stacked dielectric layer of the present invention may comprise anynumber of amorphous dielectric layers and any number of interlayerssuitable for fabricating an amorphous dielectric stacked structurehaving a desired thickness, a desired crystallization onset temperature,and/or a desired dielectric constant.

In accordance with another embodiment of the present invention,interlayer 20 may comprise multiple sublayers, which, when stacked toform interlayer 20, result in a net dielectric constant k₃ of interlayer20 that is approximately no less than the dielectric constant of HfZrO₄.Referring to FIG. 3, a semiconductor structure 100 may comprise asubstrate 12 and an oxide layer 14, such as substrate 12 and oxide layer14 described above with reference to FIG. 1. Semiconductor structure 100also may be capped with an electrode 24, such as electrode 24 describedabove with reference to FIG. 1. Semiconductor structure 100 furthercomprises an amorphous dielectric stacked structure 102 overlying oxidelayer 14. Dielectric structure 102 comprises a first amorphousdielectric layer 104 and a second amorphous dielectric layer 106. Firstamorphous dielectric layer 104 and second amorphous dielectric layer 106each may be formed of any of the materials used to form first and/orsecond dielectric layers 18 and 22 described above and may be formed ofthe same or different materials. Dielectric structure 102 may have anythickness suitable for minimizing or eliminating tunneling throughdielectric structure 102. Preferably, dielectric structure 102 has athickness in the range of about 1 nanometer to about 10 nanometers and,more preferably, has a thickness in the range of about 3 to about 4nanometers.

Dielectric structure 102 further comprises an interlayer 108 interposedbetween first and second amorphous dielectric layers 104 and 106.Interlayer 108 is formed of two or more sublayers that may have the sameor different compositions and may have the same or differentthicknesses. For example, interlayer 108 is illustrated in FIG. 3 withfour sublayers 110, 112, 114, and 116. Sublayers 110 and 114 maycomprise LaO_(X) and sublayers 112 and 116 may comprise AlO_(Y), where Xand Y are greater than zero. In this regard, sublayers 110, 112, 114,and 116 form an interlayer 108 having a net chemical compositionLa_(X)Al_(Y)O with a net dielectric constant k₃ that is approximately noless than the dielectric constant of HfZrO₄. In another example,sublayers 110 and 114 may comprise BaTiO₃ and sublayers 112 and 116 maycomprise SrTiO₃. In this regard, sublayers 110, 112, 114, and 116 forman interlayer 108 having a net chemical composition Sr_(1-X)Ba_(X)TiO₃(0≦X≦1) with a net dielectric constant k₃ that is approximately no lessthan the dielectric constant of HfZrO₄. It will be appreciated that,while FIG. 3 illustrates interlayer 108 with four sublayers, interlayer108 may comprise any suitable number of sublayers comprised of anysuitable dielectric material(s) such that the overall chemicalcomposition of interlayer 108 results in a net dielectric constant k₃that is approximately no less than the dielectric constant of HfZrO₄.

In another exemplary embodiment of the present invention, the interlayermay be “graded” that is, the chemical composition of the interlayerproximate to a first amorphous dielectric material layer is differentfrom the chemical composition of the interlayer proximate to a secondamorphous dielectric material layer, to create a dipole within theinterlayer. In this regard, the dipole may be used to modify the bandalignment of the overall semiconductor structure and, hence, theelectrode work function of the semiconductor structure. For example,referring again to FIG. 3, sublayers 110 and 114 may comprise LaO_(X)and sublayers 112 and 116 may comprise AlO_(Y), where X and Y aregreater than zero. In addition, sublayer 110 may have a thickness thatis different from the thicknesses of layers 112, 114, and 116 to createa dipole within interlayer 108. For example, sublayer 110 may havethickness of about 0.4 nanometers and sublayers 112, 114, and 116 eachmay have a thickness of about 0.2 nanometers. In this regard, sublayers110, 112, 114, and 116 form an interlayer 108 having a net chemicalcomposition La_(X)Al_(Y)O with a net dipole that modifies the bandalignment, and hence work function of the electrode 24 with respectiveto substrate 12, of the semiconductor structure 100.

FIG. 4 illustrates an energy band alignment of a semiconductor structurecomprising a hafnium oxide layer disposed between a silicon oxide layerand an electrode of a gate structure of a MOS or CMOS transistor. InFIG. 4, E_(f) is the Fermi level, V represents the valence band, Crepresents the conduction band, Vac represents the vacuum level, W(C-V)represents the work function of electrode with respect to the substrate,W(Int) is the work function of the electrode with respect to theadjacent dielectric layer, and W(Vac) is the vacuum work function of themetal electrode. Area 150 represents a band structure of a p-siliconsubstrate, area 152 represents a band structure of a silicon dioxidelayer overlying the silicon substrate, area 154 represents a bandstructure of a hafnium oxide layer overlying the silicone dioxide layer,and area 156 represents a band structure of a metal electrode overlyingthe hafnium oxide layer. In contrast, FIG. 5 illustrates an energy bandalignment of a semiconductor structure comprising a dielectric structureof the present invention, such as, for example, dielectric structure 16of FIG. 1, dielectric structure 52 of FIG. 2, or dielectric structure102 of FIG. 3. As in FIG. 4, area 150 represents a band structure of ap-silicon substrate, area 152 represents a band structure of a silicondioxide layer overlying the silicon substrate, and area 156 represents aband structure of a metal electrode. Area 158 illustrates a bandstructure of a graded dielectric structure, such as that describedabove. As is evident by comparing FIGS. 4 and 5, the band alignment ofthe semiconductor structure has been modified and the work function hasbeen adjusted by use of a graded dielectric structure.

In another exemplary embodiment, the dielectric stacked structure maycomprise a “graded” interlayer comprising a layer of material withinwhich the chemical composition changes. For example, referring again toFIG. 1, interlayer 20 may comprise a layer of material having acomposition that is graded such that the chemical composition of thelayer proximate to amorphous dielectric layer 18 is different from thechemical composition of layer proximate to amorphous dielectric layer22. Interlayer 20 may comprise a layer of La_(X)Al_(Y)O₃,La_(X)Sc_(Y)O₃, La_(X)Lu_(Y)O₃, Sr_(X)Ti_(Y)O₃, Ba_(X)Ti_(Y)O₃,Sr_(X)Ba_(Y)TiO₃, Ba_(X)Zr_(Y)O₃, or Sr_(X)Zr_(Y)O₃, where X and/or Yincreases or decreases throughout the layer or portions of the layer.

Referring now to FIG. 6, a process 200 for fabricating a semiconductorstructure in accordance with an exemplary embodiment of the presentinvention will now be provided. The semiconductor structure may be aportion of a field effect transistor or may comprise any other suitablecircuit. The process comprises the step 202 of depositing a firstamorphous dielectric layer overlying a substrate. The substrate maycomprise any of the materials described above for substrate 12 ofFIG. 1. The first amorphous dielectric layer comprises an amorphousmaterial having the formula Hf_(X)Zr_(1-X)O₂, where 0≦X≦1, and has adielectric constant k₁ that is approximately no less than the dielectricconstant of HfZrO₄. The first amorphous dielectric layer is deposited toany suitable thickness that is less than a thickness at which apolycrystalline phase may form.

In one optional embodiment of the invention, process 200 may include astep 204 of forming an oxide on the surface of the substrate before step202 is performed. In one embodiment of the invention, the substrate maybe exposed to oxygen or oxygen containing species to form the oxide. Inanother embodiment of the invention, an oxide layer may be depositedoverlying the substrate.

After formation of the first amorphous dielectric layer, an interlayeris formed overlying the first amorphous dielectric layer (step 206). Asdescribed above, the interlayer may be formed of one layer or may beformed of multiple layers with different chemical compositions and,optionally, different thicknesses. The interlayer also may be formed soas to be “graded”, as described above. The interlayer may comprise anyamorphous dielectric material or materials that results in theinterlayer having a net dielectric constant that is approximately noless than the dielectric constant of HfZrO₄. As described above,materials suitable for forming the interlayer include, but are notlimited to, lanthanum aluminum oxide (La_(X)Al_(Y)O₃), lanthanumscandium oxide (La_(X)Sc_(Y)O₃), lanthanum lutetium oxide(La_(X)Lu_(Y)O₃), strontium titanate (Sr_(X)Ti_(Y)O₃), barium titanate(Ba_(X)Ti_(Y)O₃), strontium barium titanate (Sr_(X)Ba_(Y)Ti_(Z)O₃),barium zirconium oxide (Ba_(X)Zr_(Y)O₃), strontium zirconium oxide(Sr_(X)Zr_(Y)O₃), and tantalum oxide (Ta₂O₅), where X, Y and Z are anynumbers greater than zero. The interlayer is deposited to a thicknessthat is less than a thickness at which a polycrystalline phase may form.

Next, a second amorphous dielectric layer is deposited overlying theinterlayer (step 208). The second amorphous dielectric layer comprisesan amorphous material having the formula Hf_(Y)Zr_(1-Y)O₂, where 0≦Y≦1,and has a dielectric constant k₂ that is approximately no less than thedielectric constant of HfZrO₄. In one embodiment of the invention, thefirst and second amorphous dielectric layers are formed of differentmaterials, that is, X does not equal Y and/or k₁ does not equal k₂. Inanother embodiment of the invention, the first and second amorphousdielectric layers are formed of the same materials, that is, X isapproximately equal to Y and k₁ is approximately equal to k₂. In apreferred embodiment of the invention, the first amorphous dielectriclayer and the second amorphous dielectric layer 22 comprise HfO₂. Thesecond amorphous dielectric layer is deposited to any suitable thicknessthat is less than a thickness at which a polycrystalline phase may form.

The amorphous dielectric layers and the interlayers may be formed by anysuitable process, such as molecular beam deposition (MBD), chemicalvapor deposition (CVD), physical vapor deposition (PVD), ion beamdeposition (IBD), atomic layer deposition (ALD), the like, or anycombination thereof. Preferably, the layers are formed at temperaturesfrom about 15° C. to about 350° C. After deposition of the secondamorphous dielectric layer, the dielectric stack structure is subjectedto an anneal at a temperature in the range of about 400° C. to about700° C., preferably about 500° C., in an oxygen and/or nitrogen richenvironment (step 210).

In one embodiment of the present invention, after the post-depositionanneal, an electrode layer may deposited overlying the second amorphousdielectric layer (step 212). The semiconductor structure then may besubjected to a high-temperature anneal at a temperature in the range ofabout 700° C. to about 1050° C., as is well known in the semiconductorindustry. It will be appreciated that, if the semiconductor structure isa field effect transistor, a source region and a drain region may alsobe formed within the substrate. The source and/or drain regions may beformed before or after formation of the stacked dielectric structure.

In an optional embodiment of the present invention, after deposition ofthe second amorphous dielectric layer and before the anneal, a secondinterlayer may be formed overlying the second amorphous dielectriclayer. The second interlayer may have a chemical composition that is thesame as or different from the chemical composition of the firstinterlayer described above. Similarly, the second interlayer may have athickness that is the same as or different from the thickness of thefirst interlayer. After deposition of the second interlayer, a thirdamorphous dielectric layer may be deposited. The third amorphousdielectric layer may have a chemical composition that is the same as ordifferent from the chemical compositions of the first and/or secondamorphous dielectric layers described above. Similarly, the thirdamorphous dielectric layer may have a thickness that is the same as ordifferent from the thicknesses of the first and/or second amorphousdielectric layers. It will be appreciated that any suitable number ofadditional interlayers and additional amorphous dielectric layerssubsequently may be deposited to form the dielectric stacked structure.

Accordingly, semiconductor structures and methods for formingsemiconductor structures comprising amorphous stacked structures havinghigh dielectric constants have been described. The amorphous stackedstructures may fabricated with a thickness that minimizes or eliminatestunneling through stacked structure while also preventing or minimizingthe formation of polycrystalline phases within stacked structure. Inaddition, the stacked structure exhibits an increased crystallizationonset temperature, thus improving the stability and performance of theamorphous dielectric stack during subsequent anneal processes.

In summary, structures and methods configured in accordance with exampleembodiments of the invention relate to:

A stacked dielectric structure comprising: a first amorphous dielectriclayer comprising Hf_(X)Zr_(1-X)O₂, wherein 0≦X≦1; a first amorphousinterlayer overlying said first amorphous dielectric layer, said firstinterlayer having a net dielectric constant approximately no less thanthe dielectric constant of HfZrO₄; and a second amorphous dielectriclayer overlying said first amorphous interlayer, said second amorphousdielectric layer comprising Hf_(Y)Zr_(1-Y)O₂, where 0≦Y≦1, wherein thestacked dielectric structure has a net dielectric constant that isapproximately no less than the dielectric constant of HfZrO₄. Thestacked dielectric structure further may comprise: a second amorphousinterlayer overlying said second amorphous dielectric layer, said secondamorphous interlayer having a net dielectric constant approximately noless than the dielectric constant of HfZrO₄; and a third amorphousdielectric layer overlying said second amorphous interlayer, said thirdamorphous dielectric layer comprising Hf_(N)Zr_(1-N)O₂, where 0≦N≦1. Thefirst amorphous dielectric layer and the second amorphous dielectriclayer of the stacked dielectric structure each further may compriseHfO₂. The first amorphous interlayer may comprise a material selectedfrom the group consisting of lanthanum aluminum oxide (La_(X)Al_(Y)O₃),lanthanum scandium oxide (La_(X)Sc_(Y)O₃), lanthanum lutetium oxide(La_(X)Lu_(Y)O₃), strontium titanate (Sr_(X)Ti_(Y)O₃), barium titanate(Ba_(X)Ti_(Y)O₃), strontium barium titanate (Sr_(X)Ba_(Y)Ti_(Z)O₃),barium zirconium oxide (Ba_(X)Zr_(Y)O₃), strontium zirconium oxide(Sr_(X)Zr_(Y)O₃), tantalum oxide (Ta₂O₅), and combinations thereof,wherein X, Y and Z are any numbers greater than zero. The firstamorphous interlayer also may comprise a first sublayer and a secondsublayer, wherein said first sublayer has a chemical composition that isdifferent from a chemical composition of said second sublayer. The firstsublayer further may have a thickness that is different from a thicknessof said second sublayer. The stacked dielectric structure may have athickness in the range of about 1 to about 10 nanometers.

A process for fabricating a transistor, the process comprising:depositing a first amorphous dielectric layer overlying a substrate,said first amorphous dielectric layer comprising Hf_(X)Zr_(1-X)O₂,wherein 0≦X≦1; forming an amorphous interlayer overlying said firstamorphous dielectric layer, said amorphous interlayer having a netdielectric constant approximately no less than the dielectric constantof HfZrO₄; and depositing a second amorphous dielectric layer overlyingsaid amorphous interlayer to form a stacked dielectric structure, saidsecond amorphous dielectric layer comprising Hf_(Y)Zr_(1-Y)O₂, where0≦Y≦1, wherein the stacked dielectric structure has a net dielectricconstant that is approximately no less than the dielectric constant ofHfZrO₄; and forming a source region and a drain region within saidsubstrate. The process further may comprise: forming a second amorphousinterlayer overlying said second amorphous dielectric layer, said secondamorphous interlayer having a net dielectric constant approximately noless than the dielectric constant of HfZrO₄; and depositing a thirdamorphous dielectric layer overlying said second amorphous interlayer,said third amorphous dielectric layer comprising Hf_(N)Zr_(1-N)O₂,wherein 0≦N≦1. The step of depositing a first amorphous dielectric layermay comprise the step of depositing a first amorphous layer of HfO₂. Thestep of forming said first amorphous interlayer may comprise the step ofdepositing a material selected from the group consisting of lanthanumaluminum oxide (La_(X)Al_(Y)O₃), lanthanum scandium oxide(La_(X)Sc_(Y)O₃), lanthanum lutetium oxide (La_(X)Lu_(Y)O₃), strontiumtitanate (Sr_(X)Ti_(Y)O₃), barium titanate (Ba_(X)Ti_(Y)O₃), strontiumbarium titanate (Sr_(X)Ba_(Y)Ti_(Z)O₃), tantalum oxide (Ta₂O₅), bariumzirconium oxide (Ba_(X)Zr_(Y)O₃), strontium zirconium oxide(Sr_(X)Zr_(Y)O₃), and combinations thereof, wherein X, Y and Z are anynumbers greater than zero. The step of forming said first amorphousinterlayer may comprise: forming a first sublayer having a firstchemical composition; and forming a second sublayer having a secondchemical composition that is different from said first chemicalcomposition. The step of forming said first amorphous interlayer alsomay comprise: forming said first sublayer having a first thickness; andforming said second sublayer having a second thickness that is differentfrom said first thickness. The step of forming said first amorphousinterlayer may comprise forming said first amorphous interlayer so thatsaid first amorphous interlayer has a chemical composition at a firstsurface of said amorphous interlayer that is different from a chemicalcomposition at a second surface. The steps of depositing a firstamorphous dielectric layer, forming an amorphous interlayer, anddepositing a second amorphous dielectric layer may be performed so thatthe stacked dielectric structure has a thickness in the range of about 1to about 10 nanometers.

A method for modifying a work function of a gate structure of atransistor, the method comprising: forming a layer of SiO_(X) overlyinga silicon substrate, where X is any number greater than zero; depositinga first amorphous dielectric layer of material comprisingHf_(Y)Zr_(1-Y)O₂ overlying said layer of SiO_(X), where 0≦Y≦1; formingan amorphous interlayer overlying said first amorphous dielectric layer,wherein said amorphous interlayer has a net dielectric constantapproximately no less than the dielectric constant of HfZrO₄ and whereinsaid amorphous interlayer has a chemical composition at a first surfaceof said amorphous interlayer that is different from a chemicalcomposition at a second surface of said amorphous interlayer; depositinga second amorphous dielectric layer of material comprisingHf_(Z)Zr_(1-Z)O₂ overlying said amorphous interlayer, where 0≦Z≦1; anddepositing a metal layer overlying said second amorphous dielectriclayer. The step of depositing said first amorphous dielectric layer maycomprise the step of depositing a first amorphous layer of HfO₂. Thestep of forming said amorphous interlayer may comprise the step ofdepositing a material selected from the group consisting of lanthanumaluminum oxide (La_(X)Al_(Y)O₃), lanthanum scandium oxide(La_(X)Sc_(Y)O₃), lanthanum lutetium oxide (La_(X)Lu_(Y)O₃), strontiumtitanate (Sr_(X)Ti_(Y)O₃), barium titanate (Ba_(X)Ti_(Y)O₃), strontiumbarium titanate (Sr_(X)Ba_(Y)Ti_(Z)O₃), barium zirconium oxide(Ba_(X)Zr_(Y)O₃), strontium zirconium oxide (Sr_(X)Zr_(Y)O₃), andcombinations thereof, wherein X, Y and Z are any numbers greater thanzero. The step of forming said amorphous interlayer may comprise:forming a first sublayer having a first chemical composition; andforming a second sublayer having a second chemical composition that isdifferent from said first chemical composition. The step of forming saidamorphous interlayer also may comprise: forming said first sublayerhaving a first thickness; and forming said second sublayer having asecond thickness that is different from said first thickness.

While at least one exemplary embodiment has been presented in theforegoing detailed description of the invention, it should beappreciated that a vast number of variations exist. It should also beappreciated that the exemplary embodiment or exemplary embodiments areonly examples, and are not intended to limit the scope, applicability,or configuration of the invention in any way. Rather, the foregoingdetailed description will provide those skilled in the art with aconvenient road map for implementing an exemplary embodiment of theinvention, it being understood that various changes may be made in thefunction and arrangement of elements described in an exemplaryembodiment without departing from the scope of the invention as setforth in the appended claims and their legal equivalents.

1. A process for fabricating a transistor, the process comprising:depositing a first amorphous dielectric layer overlying a substrate,said first amorphous dielectric layer comprising Hf_(X)Zr_(i-X)O₂,wherein 0≦X≦1; forming an amorphous interlayer overlying said firstamorphous dielectric layer, said amorphous interlayer having a netdielectric constant approximately no less than the dielectric constantof HfZrO₄, wherein said amorphous interlayer is formed such that achemical composition at a first surface of said amorphous interlayer isdifferent from a chemical composition at a second surface of saidamorphous interlayer; depositing a second amorphous dielectric layeroverlying said amorphous interlayer to form a stacked dielectricstructure, said second amorphous dielectric layer comprisingHfZr_(1-Y)O₂, where 0≦Y≦1, wherein the stacked dielectric structure hasa net dielectric constant that is approximately no less than thedielectric constant of HfZrO₄; forming a source region within saidsubstrate; and forming a drain region within said substrate.
 2. Theprocess for fabricating a transistor of claim 1, the process furthercomprising: forming a second amorphous interlayer overlying said secondamorphous dielectric layer, said second amorphous interlayer having anet dielectric constant approximately no less than the dielectricconstant of HfArO₄; and depositing a third amorphous dielectric layeroverlying said second amorphous interlayer, said third amorphousdielectric layer comprising Hf_(N)Zr_(1-N)O₂, wherein 0≦N≦1.
 3. Theprocess for fabricating a transistor of claim 1, wherein the step ofdepositing a first amorphous dielectric layer comprises the step ofdepositing a first amorphous layer of HfO₂.
 4. The process forfabricating a transistor of claim 1, wherein the step of forming saidfirst amorphous interlayer comprises the step of depositing a materialselected from the group consisting of lanthanum aluminum oxide(La_(X)Al_(Y)O₃), lanthanum scandium oxide (La_(X)Sc_(Y)O₃), lanthanumlutetium oxide (La_(XLu) _(Y)O₃), strontium titanate (Sr_(X)Ti_(Y)O₃),barium titanate (Ba_(X)Ti_(Y)O₃), strontium barium titanate(Sr_(X)Ba_(Y)Ti_(Z)O₃), tantalum oxide (Ta₂O₅), barium zirconium oxide(Ba_(X)Zr_(Y)O₃), strontium zirconium oxide (Sr_(X)Zr_(Y)O₃), andcombinations thereof, wherein X, Y and Z are any numbers greater thanzero.
 5. The process for fabricating a transistor of claim 1, whereinthe step of forming said first amorphous interlayer comprises: forming afirst sublayer having a first chemical composition; and forming a secondsublayer having a second chemical composition that is different fromsaid first chemical composition.
 6. The process for fabricating atransistor of claim 5, wherein the step of forming said first amorphousinterlayer comprises: forming said first sublayer having a firstthickness; and forming said second sublayer having a second thicknessthat is different from said first thickness.
 7. The process forfabricating a transistor of claim 1, wherein the step of forming saidfirst amorphous interlayer comprises forming said first amorphousinterlayer so that said first amorphous interlayer has a chemicalcomposition at a first surface of said amorphous interlayer that isdifferent from a chemical composition at a second surface.
 8. Theprocess for fabricating a transistor of claim 1, wherein the steps ofdepositing a first amorphous dielectric layer, forming an amorphousinterlayer, and depositing a second amorphous dielectric layer areperformed so that the stacked dielectric structure has a thickness inthe range of about 1 to about 10 nanometers.
 9. A method for modifying awork function of a gate structure of a transistor, the methodcomprising: forming a layer of SiO_(X) overlying a silicon substrate,where X is any number greater than zero; depositing a first amorphousdielectric layer of material comprising Hf_(Y)Zr_(1-Y)O₂ overlying saidlayer of SiO_(X), where 0≦Y≦1; forming an amorphous interlayer overlyingsaid first amorphous dielectric layer, wherein said amorphous interlayerhas a net dielectric constant approximately no less than the dielectricconstant of HfArO₄and wherein said amorphous interlayer has a chemicalcomposition at a first sin-face of said amorphous interlayer that isdifferent from a chemical composition at a second surface of saidamorphous interlayer; depositing a second amorphous dielectric layer ofmaterial comprising Hf_(z)Zr_(1-Z)O₂ overlying said amorphousinterlayer, where 0≦Z≦1; and depositing a metal layer overlying saidsecond amorphous dielectric layer.
 10. The method for modifying a workfunction of a gate structure of a transistor of claim 9, wherein thestep of depositing said first amorphous dielectric layer comprises thestep of depositing a first amorphous layer of HfO₂.
 11. The method formodifying a work function of a gate structure of a transistor of claim9, wherein the step of forming said amorphous interlayer comprises thestep of depositing a material selected from the group consisting oflanthanum aluminum oxide (La_(X)Al_(Y)O₃), lanthanum scandium oxide(La_(X)Sc_(Y)O₃), lanthanum lutetium oxide (La_(X)Lu_(Y)O₃), strontiumtitanate (Sr_(X)Ti_(Y)O₃), barium titanate (Ba_(X)Ti_(Y)O₃), strontiumbarium titanate (Sr_(X)Ba_(Y)Ti_(Z)O₄ barium zirconium oxide(Ba_(X)Zr_(Y)O₃), strontium zirconium oxide (Sr_(X)Zr_(Y)O₃), andcombinations thereof, wherein X, Y and Z are any numbers greater thanzero.
 12. The method for modifying a work function of a gate structureof a transistor of claim 9, wherein the step of fanning said amorphousinterlayer comprises: forming a first sublayer having a first chemicalcomposition; and forming a second sublayer having a second chemicalcomposition that is different from said first chemical composition. 13.The method for modifying a work function of a gate structure of atransistor of claim 12, wherein the step of forming said amorphousinterlayer comprises: forming said first sublayer having a firstthickness; and forming said second sublayer having a second thicknessthat is different from said first thickness.